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exar corporation, 48720 kato road, fremont, ca 94538 (510) 668-7000 fax (510) 668-7017 ST16C554/554d st68c554 rev. 3.10 plcc package quad uart with 16-byte fifo?s description the ST16C554d is a universal asynchronous receiver and transmitter (uart) with a dual foot print interface. the 554d is an enhanced uart with 16 byte fifos, receive trigger levels and data rates up to 1.5mbps. onboard status registers provide the user with error indications and operational status, modem interface control. system interrupts may be tailored to meet user requirements. an internal loopback capability allows onboard diagnostics. the 554d is available in 64 pin tqfp, and 68 pin plcc packages. the 68 pin plcc package offer an additional 68 mode which allows easy integration with motorola, and other popu- lar microprocessors. the ST16C554cq64 (64 pin) offers three state interrupt control while the ST16C554dcq64 provides constant active interrupt outputs. the 64 pin devices do not offer txrdy/ rxrdy outputs. the 554d combines the package interface modes of the 16c554 and 68c554 series on a single integrated chip. features compatibility with the industry standard st16c454, st68c454, st68c554, tl16c554 1.5 mbps transmit/receive operation (24mhz) 16 byte transmit fifo 16 byte receive fifo with error flags independent transmit and receive control software selectable baud rate generator four selectable receive fifo interrupt trigger levels standard modem interface ordering information part number pins package o perating temperature ST16C554dcj68 68 plcc 0 c to + 70 c ST16C554dcq64 64 tqfp 0 c to + 70 c ST16C554cq64 64 tqfp 0 c to + 70 c ST16C554dij68 68 plcc -40 c to + 85 c ST16C554diq64 64 tqfp -40 c to + 85 c 9 8 7 6 5 4 3 2 1 68 67 66 65 64 63 62 61 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 -dsra -ctsa -dtra vcc -rtsa inta -csa txa -iow txb -csb intb -rtsb gnd -dtrb -ctsb -dsrb -cdb -rib rxb vcc 16/-68 a2 a1 a0 xtal1 xtal2 reset -rxrdy -txrdy gnd rxc -ric -cdc -dsrd -ctsd -dtrd gnd -rtsd intd -csd txd -ior txc -csc intc -rtsc vcc -dtrc -ctsc -dsrc -cda -ria rxa gnd d7 d6 d5 d4 d3 d2 d1 d0 intsel vcc rxd -rid -cdd ST16C554dcj68 16 mode
ST16C554/554d/68c554 2 rev. 3.10 64 pin tqfp package 68 pin plcc package figure 1, package descriptions 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 -dsra -ctsa -dtra vcc -rtsa inta -csa txa -iow -txb -csb intb -rtsb gnd -dtrb -ctsb -dsrb -cdb -rib rxb vcc a2 a1 a0 xtal1 xtal2 reset gnd rxc -ric -cdc -dsrc -dsrd -ctsd -dtrd gnd -rtsd intd -csd txd -ior txc -csc intc -rtsc vcc -dtrc -ctsc -cda -ria rxa gnd d7 d6 d5 d4 d3 d2 d1 d0 vcc rxd -rid -cdd ST16C554cq64 ST16C554dcq64 9 8 7 6 5 4 3 2 1 68 67 66 65 64 63 62 61 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 -dsra -ctsa -dtra vcc -rtsa -irq -cs txa r/-w txb a3 n.c. -rtsb gnd -dtrb -ctsb -dsrb -cdb -rib rxb vcc 16/-68 a2 a1 a0 xtal1 xtal2 -reset -rxrdy -txrdy gnd rxc -ric -cdc -dsrd -ctsd -dtrd gnd -rtsd n.c. n.c. txd n.c. txc a4 n.c. -rtsc vcc -dtrc -ctsc -dsrc -cd a -ria rxa gnd d7 d6 d5 d4 d3 d2 d1 d0 n.c. vcc rxd -rid -cd d ST16C554dcj68 68 mode
ST16C554/554d/68c554 3 rev. 3.10 figure 2, block diagram 16 mode d0-d7 -ior -iow reset a0-a2 -cs a-d i nt a-d -rxrdy -txrdy intsel -dtr a-d -rts a-d -cts a-d -ri a-d -cd a-d -dsr a-d tx a-d rx a-d xtal1 xtal2 data bus & control logic register select logic modem control logic interrupt control logic transmit fifo registers transmit shift register receive fifo registers receive shift register inter connect bus lines & control signals clock & baud rate generator
ST16C554/554d/68c554 4 rev. 3.10 figure 3, block diagram 68 mode d0-d7 r/-w -reset a0-a4 -cs -irq -rxrdy -txrdy -dtr a-d -rts a-d -cts a-d -ri a-d -cd a-d -dsr a-d tx a-d rx a-d xtal1 xtal2 data bus & control logic register select logic modem control logic interrupt control logic transmit fifo registers transmit shift register receive fifo registers receive shift register inter connect bus lines & control signals clock & baud rate generator
ST16C554/554d/68c554 5 rev. 3.10 symbol description symbol pin signal pin description 68 64 type 16/-68 31 - i 16/68 interface type select (input with internal pull-up). - this input provides the 16 (intel) or 68 (motorola) bus interface type select. the functions of -ior, -iow, int a- d, and -cs a-d are re-assigned with the logical state of this pin. when this pin is a logic 1, the 16 mode interface 16c554d is selected. when this pin is a logic 0, the 68 mode interface (68c554) is selected. when this pin is a logic 0, - iow is re-assigned to -r/w, reset is re-assigned to - reset, -ior is not used, and int a-d(s) are connected in a wire-or? configuration. the wire-or outputs are connected internally to the open source irq signal output. this pin is not available on 64 pin packages which operate in the 16 mode only. a0 34 24 i address-0 select bit. internal registers address selection in 16 and 68 modes. a1 33 23 i address-1 select bit. internal registers address selection in 16 and 68 modes. a2 32 22 i address-2 select bit. - internal registers address selection in 16 and 68 modes. a3-a4 20,50 - i address 3-4 select bits. - when the 68 mode is selected, these pins are used to address or select individual uart?s (providing -cs is a logic 0). in the 16 mode, these pins are reassigned as chip selects, see -csb and -csc. these pins are not available on 64 pin packages which operate in the 16 mode only. -cs 16 - i chip select. (active low) - in the 68 mode, this pin functions as a multiple channel chip enable. in this case, all four uarts (a-d) are enabled when the -cs pin is a logic 0. an individual uart channel is selected by the data contents of address bits a3-a4. when the 16 mode is selected (68 pin device), this pin functions as -csa, see definition under -cs a-b. this pin is not available on 64 pin packages which operate in the 16 mode only.
ST16C554/554d/68c554 6 rev. 3.10 symbol description symbol pin signal pin description 68 64 type -cs a-b 16,20 7,11 -cs c-d 50,54 38,42 i chip select a, b, c, d (active low) - this function is associated with the 16 mode only, and for individual chan- nels, ?a? through ?d.? when in 16 mode, these pins enable data transfers between the user cpu and the ST16C554d for the channel(s) addressed. individual uart sections (a, b, c, d) are addressed by providing a logic 0 on the respective -cs a-d pin. when the 68 mode is selected, the functions of these pins are reassigned. 68 mode functions are described under the their respective name/pin head- ings. d0-d2 66-68 53-55 i/o d3-d7 1-5 56-60 data bus (bi-directional) - these pins are the eight bit, three state data bus for transferring information to or from the controlling cpu. d0 is the least significant bit and the first data bit in a transmit or receive serial data stream. gnd 6,23 14,28 gnd 40,57 45,61 pwr signal and power ground. int a-b 15,21 6,12 int c-d 49,55 37,43 o interrupt a, b, c, d (active high) - this function is associated with the 16 mode only. these pins provide individual channel interrupts, int a-d. int a-d are enabled when mcr bit-3 is set to a logic 1, interrupts are enabled in the interrupt enable register (ier), and when an interrupt con- dition exists. interrupt conditions include: receiver errors, available receiver buffer data, transmit buffer empty, or when a modem status flag is detected. when the 68 mode is selected, the functions of these pins are reassigned. 68 mode functions are described under the their respective name/pin headings. intsel 65 - i interrupt select. (active high, with internal pull-down) - this function is associated with the 16 mode only. when the 16 mode is selected, this pin can be used in conjunction with mcr bit-3 to enable or disable the three state interrupts, int a-d or override mcr bit-3 and force continuous interrupts. interrupt outputs are enabled continuously by making this
ST16C554/554d/68c554 7 rev. 3.10 symbol description symbol pin signal pin description 68 64 type pin a logic 1. making this pin a logic 0 allows mcr bit-3 to control the three state interrupt output. in this mode, mcr bit-3 is set to a logic ?1? to enable the three state outputs. this pin is disabled in the 68 mode. due to pin limitations on 64 pin packages, this pin is not available. to cover this limitation, two 64 pin qfp package versions are offered. the ST16C554dcq64 operates in the continuos interrupt enable mode by bonded this pin to vcc internally. the ST16C554cq64 operates with mcr bit-3 control by bond- ing this pin to gnd. -ior 52 40 i read strobe. (active low strobe) - this function is associ- ated with the 16 mode only. a logic 0 transition on this pin will load the contents of an internal register defined by address bits a0-a2 onto the ST16C554d data bus (d0-d7) for access by an external cpu. this pin is disabled in the 68 mode. -iow 18 9 i w rite strobe. (active low strobe) - this function is associ- ated with the 16 mode only. a logic 0 transition on this pin will transfer the contents of the data bus (d0-d7) from the external cpu to an internal register that is defined by address bits a0/a2. when the 16 mode is selected, this pin functions as -r/w, see definition under r/w. -irq 15 - o interrupt request or interrupt ?a? - this function is associ- ated with the 68 mode only. in the 68 mode, interrupts from uart channels a-d are wire-or?ed? internally to function as a single irq interrupt. this pin transitions to a logic 0 (if enabled by the interrupt enable register) whenever a uart channel(s) requires service. individual channel interrupt status can be determined by addressing each channel through its associated internal register, using -cs and a3- a4. in the 68 mode an external pull-up resistor must be connected between this pin and vcc. the function of this pin changes to inta when operating in the 16 mode, see definition under inta.
ST16C554/554d/68c554 8 rev. 3.10 symbol description symbol pin signal pin description 68 64 type -reset reset 37 27 i reset. - in the 16 mode a logic 1 on this pin will reset the internal registers and all the outputs. the uart transmitter output and the receiver input will be disabled during reset time. (see ST16C554d external reset conditions for ini- tialization details.) when 16/-68 is a logic 0 (68 mode), this pin functions similarly but, as an inverted reset interface signal, -reset. -r/w 18 - i read/write strobe (active low) - this function is associated with the 68 mode only. this pin provides the combined functions for read or write strobes. a logic 1 to 0 transition transfers the contents of the cpu data bus (d0-d7) to the register selected by -cs and a0-a4. similarly a logic 0 to 1 transition places the contents of a 554d register selected by -cs and a0-a4 on the data bus, d0-d7, for transfer to an external cpu. -rxrdy 38 - o receive ready (active low) - this function is associated with 68 pin packages only. -rxrdy contains the wire ?or- ed? status of all four receive channel fifos, rxrdy a-d. a logic 0 indicates receive data ready status, i.e. the rhr is full or the fifo has one or more rx characters available for unloading. this pin goes to a logic 1 when the fifo/rhr is full or when there are no more characters available in either the fifo or rhr. for 64/68 pin packages, individual channel rx status is read by examining individual internal registers via -cs and a0-a4 pin functions. -txrdy 39 - o transmit ready (active low) - this function is associated with 68 pin package only. -txrdy contains the wire ?or- ed? status of all four transmit channel fifos, txrdy a-d. a logic 0 indicates a buffer ready status, i.e., at least one location is empty and available in one of the tx channels (a- d). this pin goes to a logic 1 when all four channels have no more empty locations in the tx fifo or thr. vcc 13 4,21 vcc 47,64 35,52 i power supply inputs.
ST16C554/554d/68c554 9 rev. 3.10 symbol description symbol pin signal pin description 68 64 type xtal1 35 25 i crystal or external clock input - functions as a crystal input or as an external clock input. a crystal can be connected between this pin and xtal2 to form an internal oscillator circuit (see figure 8). alternatively, an external clock can be connected to this pin to provide custom data rates (see baud rate generator programming). xtal2 36 26 o output of the crystal oscillator or buffered clock - (see also xtal1). crystal oscillator output or buffered clock output. -cd a-b 9,27 64,18 -cd c-d 43,61 31,49 i carrier detect (active low) - these inputs are associated with individual uart channels a through d. a logic 0 on this pin indicates that a carrier has been detected by the modem for that channel. -cts a-b 11,25 2,16 -cts c-d 45,59 33,47 i clear to send (active low) - these inputs are associated with individual uart channels, a through d. a logic 0 on the - cts pin indicates the modem or data set is ready to accept transmit data from the 554d. status can be tested by reading msr bit-4. -dsr a-b 10,26 1,17 -dsr c-d 44,60 32,48 i data set ready (active low) - these inputs are associated with individual uart channels, a through d. a logic 0 on this pin indicates the modem or data set is powered-on and is ready for data exchange with the uart. this pin has no effect on the uart?s transmit or receive operation. this pin has no effect on the uart?s transmit or receive operation. -dtr a-b 12,24 3,15 -dtr c-d 46,58 34,46 o data terminal ready (active low) - these inputs are associated with individual uart channels, a through d. a logic 0 on this pin indicates that the 554d is powered-on and ready. this pin can be controlled via the modem control register. writing a logic 1 to mcr bit-0 will set the -dtr output to logic 0, enabling the modem. this pin will be a logic 1 after writing a logic 0 to mcr bit-0. this pin has no effect on the uart?s transmit or receive operation.
ST16C554/554d/68c554 10 rev. 3.10 symbol pin signal pin description 68 64 type symbol description -ri a-b 8,28 63,19 -ri c-d 42,62 30,50 i ring indicator (active low) - these inputs are associated with individual uart channels, a through d. a logic 0 on this pin indicates the modem has received a ringing signal from the telephone line. a logic 1 transition on this input pin will generate an interrupt. -rts a-b 14,22 5,13 -rts c-d 48,56 36,44 o request to send (active low) - these outputs are associated with individual uart channels, a through d. a logic 0 on the -rts pin indicates the transmitter has data ready and waiting to send. writing a logic 1 in the modem control register (mcr bit-1) will set this pin to a logic 0 indicating data is available. after a reset this pin will be set to a logic 1. this pin has no effect on the uart?s transmit or receive operation. rx a-b 7,29 62,20 rx c-d 41,63 29,51 i receive data input rx a-d. - these inputs are associated with individual serial channel data to the ST16C554d. the rx signal will be a logic 1 during reset, idle (no data), or when the transmitter is disabled. during the local loopback mode, the rx input pin is disabled and tx data is internally connected to the uart rx input, internally. tx a-b 17,19 8,10 tx c-d 51,53 39,41 o transmit data - these outputs are associated with indi- vidual serial transmit channel data from the 554d. the tx signal will be a logic 1 during reset, idle (no data), or when the transmitter is disabled. during the local loopback mode, the tx input pin is disabled and tx data is internally connected to the uart rx input.
ST16C554/554d/68c554 11 rev. 3.10 general description the 554d provides serial asynchronous receive data synchronization, parallel-to-serial and serial-to-paral- lel data conversions for both the transmitter and receiver sections. these functions are necessary for converting the serial data stream into parallel data that is required with digital data systems. synchronization for the serial data stream is accomplished by adding start and stops bits to the transmit data to form a data character (character orientated protocol). data integ- rity is insured by attaching a parity bit to the data character. the parity bit is checked by the receiver for any transmission bit errors. the electronic circuitry to provide all these functions is fairly complex especially when manufactured on a single integrated silicon chip. the ST16C554d represents such an integration with greatly enhanced features. the 554d is fabri- cated with an advanced cmos process to achieve low drain power and high speed requirements. the 554d is an upward solution that provides 16 bytes of transmit and receive fifo memory, instead of 1 bytes provided in the 16/68c454. the 554d is de- signed to work with high speed modems and shared network environments, that require fast data process- ing time. increased performance is realized in the 554d by the larger transmit and receive fifos. this allows the external processor to handle more network- ing tasks within a given time. this increases the service interval giving the external cpu additional time for other applications and reducing the overall uart interrupt servicing time. the 554d combines the package interface modes of the 16c554d and 68c554 series on a single inte- grated chip. the 16 mode interface is designed to operate with the intel type of microprocessor bus while the 68 mode is intended to operate with motorola, and other popular microprocessors. following a reset, the 554d is down-ward compatible with the st16c454/ st68c454 dependent on the state of the interface mode selection pin, 16/-68. the 554d is capable of operation to 1.5mbps with a 24 mhz crystal or external clock input. with a crystal of 14.7464 mhz, the user can select data rates up to 921.6kbps. the rich feature set of the 554d is available through internal registers. selectable receive fifo trigger levels, selectable tx and rx baud rates, modem interface controls. in the 16 mode intsel and mcr bit-3 can be configured to provide a software con- trolled or continuous interrupt capability. due of pin limitations for the 64 pin 554d this feature is offered by two different qfp packages. the ST16C554dcq64 operates in the continuos interrupt enable mode by bonded intsel to vcc internally. the ST16C554cq64 operates in conjunction with mcr bit-3 by bonding intsel to gnd internally. functional descriptions interface options two user interface modes are selectable for the 554d package. these interface modes are designated as the ?16 mode? and the ?68 mode.? this nomenclature corresponds to the early 16c554d and 68c554 pack- age interfaces respectively. the 16 mode interface the 16 mode configures the package interface pins for connection as a standard 16 series (intel) device and operates similar to the standard cpu interface avail- able on the 16c554d. in the 16 mode (pin 16/-68 logic 1) each uart is selected with individual chip select (csx) pins as shown in table 2 below. table 2, serial port channel selection guide, 16 mode interface -csa -csb -csc -csd uart channel 1111 none 0111 a 1011 b 1101 c 1110 d
ST16C554/554d/68c554 12 rev. 3.10 the 68 mode interface the 68 mode configures the package interface pins for connection with motorola, and other popular micro- processor bus types. the interface operates similar to the 68c454/554. in this mode the 554d decodes two additional addresses, a3-a4 to select one of the four uart ports. the a3-a4 address decode function is used only when in the 68 mode (16/-68 logic 0), and is shown in table 3 below. table 3, serial port channel selection guide, 68 mode interface -cs a4 a3 uart channel 1 n/a n/a none 000 a 001 b 010 c 011 d internal registers the 554d provides 13 internal registers for monitoring and control. these resisters are shown in table 4 below. twelve registers are similar to those already available in the standard 16c454. these registers function as data holding registers (thr/rhr), inter- rupt status and control registers (ier/isr), line status and control registers (lcr/lsr), modem status and control registers (mcr/msr), programmable data rate (clock) control registers (dll/dlm), and a user assessable scratchpad register (spr). register func- tions are more fully described in the following para- graphs. table 4, internal register decode a2 a1 a0 read mode write mode general register set (thr/rhr, ier/isr, mcr/msr, lcr/lsr, spr): 0 0 0 receive holding register transmit holding register 0 0 1 interrupt enable register 0 1 0 interrupt status register fifo control register 0 1 1 line control register 1 0 0 modem control register 1 0 1 line status register 1 1 0 modem status register 1 1 1 scratchpad register scratchpad register baud rate register set (dll/dlm): note *2 0 0 0 lsb of divisor latch lsb of divisor latch 0 0 1 msb of divisor latch msb of divisor latch note *2: these registers are accessible only when lcr bit-7 is set to a logic 1.
ST16C554/554d/68c554 13 rev. 3.10 fifo operation the 16 byte transmit and receive data fifo?s are enabled by the fifo control register (fcr) bit-0. with 16c554 devices, the user can only set the receive trigger level. the receiver fifo section in- cludes a time-out function to ensure data is delivered to the external cpu. an interrupt is generated when- ever the receive holding register (rhr) has not been read following the loading of a character or the receive trigger level has not been reached. timeout interrupts the interrupts are enabled by ier bits 0-3. care must be taken when handling these interrupts. following a reset the transmitter interrupt is enabled, the 554d will issue an interrupt to indicate that transmit holding register is empty. this interrupt must be serviced prior to continuing operations. the lsr register provides the current singular highest priority interrupt only. servicing the interrupt without investigating further interrupt conditions can result in data errors. when two interrupt conditions have the same priority, it is important to service these interrupts correctly. receive data ready and receive time out have the same interrupt priority (when enabled by ier bit-0). the receiver issues an interrupt after the number of characters have reached the programmed trigger level. in this case the 554d fifo may hold more characters than the programmed trigger level. follow- ing the removal of a data byte, the user should recheck lsr bit-0 for additional characters. a receive time out will not occur if the receive fifo is empty. the time out counter is reset at the center of each stop bit received or each time the receive holding register (rhr) is read. the actual time out value is t ( t ime out length in bits) = 4 x p ( p rogrammed word length) + 12. to convert the time out value to a character value, the user has to consider the complete word length, includ- ing data information length, start bit, parity bit, and the size of stop bit, i.e., 1x, 1.5x, or 2x bit times. example -a: if the user programs a word length of 7, with no parity and one stop bit, the time out will be: t = 4 x 7( programmed word length) +12 = 40 bit times. the character time will be equal to 40 / 9 = 4.4 characters, or as shown in the fully worked out ex- ample: t = [(programmed word length = 7) + (stop bit = 1) + (start bit = 1) = 9]. 40 (bit times divided by 9) = 4.4 characters. example -b: if the user programs the word length = 7, with parity and one stop bit, the time out will be: t = 4 x 7(programmed word length) + 12 = 40 bit times. character time = 40 / 10 [ (programmed word length = 7) + (parity = 1) + (stop bit = 1) + (start bit = 1) = 4 characters. in the 16 mode for 68 pin packages, the system/board designer can optionally provide software controlled three state interrupt operation. this is accomplished by intsel and mcr bit-3. when intsel interface pin is left open or made a logic 0, mcr bit-3 controls the three state interrupt outputs, int a-d. when intsel is a logic 1, mcr bit-3 has no effect on the int a-d outputs and the package operates with interrupt outputs enabled continuously. programmable baud rate generator the 554d supports high speed modem technologies that have increased input data rates by employing data compression schemes. for example a 33.6kbps modem that employs data compression may require a 115.2kbps input data rate. a 128.0kbps isdn modem that supports data compression may need an input data rate of 460.8kbps. the 554d can support a standard data rate of 921.6kbps. single baud rate generator is provided for the transmitter and receiver, allowing independent tx/ rx channel control. the programmable baud rate generator is capable of accepting an input clock up to 24 mhz, as required for supporting a 1.5mbps data rate. the 554d can be configured for internal or external clock operation. for internal clock oscillator operation, an industry standard micropro- cessor crystal (parallel resonant/ 22-33 pf load) is connected externally between the xtal1 and xtal2 pins (see figure 8). alternatively, an external clock can be connected to the xtal1 pin to clock the internal baud rate generator for standard or custom rates. (see baud rate generator program- ming).
ST16C554/554d/68c554 14 rev. 3.10 the generator divides the input 16x clock by any divisor from 1 to 2 16 -1. the 554d divides the basic crystal or external clock by 16. further division of this 16x clock provides two table rates to support low and high data rate applications using the same system design. customized baud rates can be achieved by selecting the proper divisor values for the msb and lsb sections of baud rate generator. programming the baud rate generator registers dlm (msb) and dll (lsb) provides a user capability for selecting the desired final baud rate. the example in table 5 below, shows the two selectable baud rate tables available when using a 7.3728 mhz crystal. c1 22pf c2 33pf x1 1.8432 mhz xta l 1 xta l 2 figure 8, crystal oscillator connection table 5, baud rate generator programming table: output output user user dlm dll baud rate baud rate 16 x clock 16 x clock program program (1.8432 mhz (7.3728 mhz divisor divisor value value clock) clock) (decimal) (hex) (hex) (hex) 50 200 2304 900 09 00 300 1200 384 180 01 80 600 2400 192 c0 00 c0 1200 4800 96 60 00 60 2400 9600 48 30 00 30 4800 19.2k 24 18 00 18 9600 38.4k 12 0c 00 0c 19.2k 76.8k 6 06 00 06 38.4k 153.6k 3 03 00 03 57.6k 230.4k 2 02 00 02 115.2k 460.8k 1 01 00 01
ST16C554/554d/68c554 15 rev. 3.10 dma operation the 554d fifo trigger level provides additional flexibility to the user for block mode operation. lsr bits 5-6 provide an indication when the transmitter is empty or has an empty location(s). the user can optionally operate the transmit and receive fifos in the dma mode (fcr bit-3). when the transmit and receive fifos are enabled and the dma mode is deactivated (dma mode ?0?), the 554d activates the interrupt output pin for each data transmit or receive operation. when dma mode is activated (dma mode ?1?), the user takes the advantage of block mode operation by loading or unloading the fifo in a block sequence determined by the preset trigger level. in this mode, the 554d sets the interrupt output pin when characters in the transmit fifos are below the trans- mit trigger level, or the characters in the receive fifos are above the receive trigger level. loopback mode the internal loopback capability allows onboard diag- nostics. in the loopback mode the normal modem interface pins are disconnected and reconfigured for loopback internally. mcr register bits 0-3 are used for controlling loopback diagnostic testing. in the loopback mode op1 and op2 in the mcr register (bits 3/2) control the modem -ri and -cd inputs respectively. mcr signals -dtr and -rts (bits 0-1) are used to control the modem -cts and -dsr inputs respectively. the transmitter output (tx) and the receiver input (rx) are disconnected from their asso- ciated interface pins, and instead are connected to- gether internally (see figure 12). the -cts, -dsr, - cd, and -ri are disconnected from their normal modem control inputs pins, and instead are connected internally to -dtr, -rts, -op1 and -op2. loopback test data is entered into the transmit holding register via the user data bus interface, d0-d7. the transmit uart serializes the data and passes the serial data to the receive uart via the internal loopback connec- tion. the receive uart converts the serial data back into parallel data that is then made available at the user data interface, d0-d7. the user optionally com- pares the received data to the initial transmitted data for verifying error free operation of the uart tx/rx circuits. in this mode, the receiver and transmitter interrupts are fully operational. the modem control interrupts are also operational. however, the interrupts can only be read using lower four bits of the modem control register (mcr bits 0-3) instead of the four modem status register bits 4-7. the interrupts are still con- trolled by the ier.
ST16C554/554d/68c554 16 rev. 3.10 figure 12, internal loopback mode diagram d0-d7 -ior,-iow reset a0-a2 -cs a-d int a-d -rxrdy -txrdy tx a-d rx a-d data bus & control logic register select logic modem control logic interrupt control logic transmit fifo registers transmit shift register receive fifo registers receive shift register inter connect bus lines & control signals clock & baud rate generator xtal1 xtal2 -cts a-d -rts a-d -dtr a-d -dsr a-d -ri a-d -cd a-d (-op1 a-d) (-op2 a-d) mcr bit-4=1
ST16C554/554d/68c554 17 rev. 3.10 register functional descriptions the following table delineates the assigned bit functions for the fifteen 554d internal registers. the assigned bit functions are more fully defined in the following paragraphs. table 6, ST16C554d internal registers a2 a1 a0 register bit-7 bit-6 bit-5 bit-4 bit-3 bit-2 bit-1 bit-0 [note *5] general register set 0 0 0 rhr[xx] bit-7 bit-6 bit-5 bit-4 bit-3 bit-2 bit-1 bit-0 0 0 0 thr[xx] bit-7 bit-6 bit-5 bit-4 bit-3 bit-2 bit-1 bit-0 0 0 1 ier[00] 0000m odem receive transmit receive status line holding holding interrupt status register register interrupt 0 1 0 fcr rcvr rcvr 0 0 dma xmit rcvr fifo trigger trigger mode fifo fifo enable (msb) (lsb) select reset r eset 0 1 0 isr[01] fifo?s fifo?s 0 0 int int int int enabled enabled prio rity priority priority status bit-2 bit-1 bit-0 0 1 1 lcr[00] divisor set set even parity stop word word latch break parity parity enable bits l ength length enable b it-1 bit-0 1 0 0 mcr[00] 0 0 0 loop -op2/ -op1 -rts -dtr back intx enable 1 0 1 lsr[60] fifo trans. trans. break framing parity overrun receive data empty holding interrupt error error error data error empty ready 1 1 0 msr[x0] cd ri dsr cts delta delta delta delta -cd -ri -dsr -cts 1 1 1 spr[ff] bit-7 bit-6 bit-5 bit-4 bit-3 bit-2 bit-1 bit-0 special register set: note *2 0 0 0 dll[xx] bit-7 bit-6 bit-5 bit-4 bit-3 bit-2 bit-1 bit-0 0 0 1 dlm[xx] bit-15 bit-14 bit-13 bit-12 bit-11 bit-10 b it-9 bit-8 note * 2 : the special register set is accessible only when lcr bit-7 is set to ?1?.
ST16C554/554d/68c554 18 rev. 3.10 note * 5 : the value between the square brackets represents the register?s initialized hex value. transmit (thr) and receive (rhr) holding reg- isters the serial transmitter section consists of an 8-bit transmit hold register (thr) and transmit shift register (tsr). the status of the thr is provided in the line status register (lsr). writing to the thr transfers the contents of the data bus (d7-d0) to the thr, providing that the thr or tsr is empty. the thr empty flag in the lsr register will be set to a logic 1 when the transmitter is empty or when data is transferred to the tsr. note that a write operation can be performed when the transmit holding register empty flag is set (logic 0 = fifo full, logic 1= at least one fifo location available). the serial receive section also contains an 8-bit receive holding register, rhr. receive data is removed from the 554d and receive fifo by reading the rhr register. the receive section provides a mechanism to prevent false starts. on the falling edge of a start or false start bit, an internal receiver counter starts counting clocks at 16x clock rate. after 7 1/2 clocks the start bit time should be shifted to the center of the start bit. at this time the start bit is sampled and if it is still a logic 0 it is validated. evaluating the start bit in this manner prevents the receiver from assem- bling a false character. receiver status codes will be posted in the lsr. interrupt enable register (ier) the interrupt enable register (ier) masks the inter- rupts from receiver ready, transmitter empty, line status and modem status registers. these interrupts would normally be seen on the int a-d output pins in the 16 mode, or on wire-or irq output pin, in the 68 mode. ier vs receive fifo interrupt mode operation when the receive fifo (fcr bit-0 = a logic 1) and receive interrupts (ier bit-0 = logic 1) are enabled, the receive interrupts and register status will reflect the following: a) the receive data available interrupts are issued to the external cpu when the fifo has reached the programmed trigger level. it will be cleared when the fifo drops below the programmed trigger level. b) fifo status will also be reflected in the user accessible isr register when the fifo trigger level is reached. both the isr register status bit and the interrupt will be cleared when the fifo drops below the trigger level. c) the data ready bit (lsr bit-0) is set as soon as a character is transferred from the shift register to the receive fifo. it is reset when the fifo is empty. ier vs receive/transmit fifo polled mode op- eration when fcr bit-0 equals a logic 1; resetting ier bits 0-3 enables the 554d in the fifo polled mode of operation. since the receiver and transmitter have separate bits in the lsr either or both can be used in the polled mode by selecting respective transmit or receive control bit(s). a) lsr bit-0 will be a logic 1 as long as there is one byte in the receive fifo. b) lsr bit 1-4 will provide the type of errors encoun- tered, if any. c) lsr bit-5 will indicate when the transmit fifo is empty. d) lsr bit-6 will indicate when both the transmit fifo and transmit shift register are empty. e) lsr bit-7 will indicate any fifo data errors. ier bit-0: this interrupt will be issued when the fifo has reached the programmed trigger level or is cleared when the fifo drops below the trigger level in the fifo mode of operation. logic 0 = disable the receiver ready interrupt. (normal
ST16C554/554d/68c554 19 rev. 3.10 default condition) logic 1 = enable the receiver ready interrupt. ier bit-1: this interrupt will be issued whenever the thr is empty and is associated with bit-1 in the lsr register. logic 0 = disable the transmitter empty interrupt. (normal default condition) logic 1 = enable the transmitter empty interrupt. ier bit-2: this interrupt will be issued whenever a fully as- sembled receive character is transferred from the rsr to the rhr/fifo, i.e., data ready, lsr bit-0. logic 0 = disable the receiver line status interrupt. (normal default condition) logic 1 = enable the receiver line status interrupt. ier bit-3: logic 0 = disable the modem status register interrupt. (normal default condition) logic 1 = enable the modem status register interrupt. ier bit 4-7: not used - initialized to a logic 0. fifo control register (fcr) this register is used to enable the fifos, clear the fifos, set the transmit/receive fifo trigger levels, and select the dma mode. the dma, and fifo modes are defined as follows: dma mode mode 0 set and enable the interrupt for each single transmit or receive operation, and is similar to the st16c454 mode. transmit ready (-txrdy) will go to a logic 0 when ever an empty transmit space is available in the transmit holding register (thr). receive ready (-rxrdy) will go to a logic 0 when- ever the receive holding register (rhr) is loaded with a character. mode 1 set and enable the interrupt in a block mode operation. the transmit interrupt is set when the transmit fifo is below the programmed trigger level. -txrdy remains a logic 0 as long as one empty fifo location is available. the receive interrupt is set when the receive fifo fills to the programmed trigger level. however the fifo continues to fill regardless of the programmed level until the fifo is full. -rxrdy remains a logic 0 as long as the fifo fill level is above the programmed trigger level. fcr bit-0: logic 0 = disable the transmit and receive fifo. (normal default condition) logic 1 = enable the transmit and receive fifo. this bit must be a ?1? when other fcr bits are written to or they will not be programmed. fcr bit-1: logic 0 = no fifo receive reset. (normal default condition) logic 1 = clears the contents of the receive fifo and resets the fifo counter logic (the receive shift regis- ter is not cleared or altered). this bit will return to a logic 0 after clearing the fifo. fcr bit-2: logic 0 = no fifo transmit reset. (normal default condition) logic 1 = clears the contents of the transmit fifo and resets the fifo counter logic (the transmit shift regis- ter is not cleared or altered). this bit will return to a logic 0 after clearing the fifo. fcr bit-3: logic 0 = set dma mode ?0?. (normal default condi- tion) logic 1 = set dma mode ?1.? transmit operation in mode ?0?: when the 554d is in the st16c450 mode (fifos disabled, fcr bit-0 = logic 0) or in the fifo mode (fifos enabled, fcr bit-0 = logic 1, fcr bit-3 = logic 0) and when there are no characters in the transmit fifo or transmit holding register, the -txrdy pin will be a logic 0. once active the -txrdy pin will go to a logic 1 after the first character is loaded into the transmit holding register. receive operation in mode ?0?: when the 554d is in mode ?0? (fcr bit-0 = logic 0) or in the fifo mode (fcr bit-0 = logic 1, fcr bit-3 = logic 0) and there is at least one character in the receive fifo, the -rxrdy pin will be a logic 0. once active the -rxrdy pin will go to a logic 1 when there are no more characters in the receiver.
ST16C554/554d/68c554 20 rev. 3.10 transmit operation in mode ?1?: when the 554d is in fifo mode ( fcr bit-0 = logic 1, fcr bit-3 = logic 1 ), the -txrdy pin will be a logic 1 when the transmit fifo is completely full. it will be a logic 0 if one or more fifo locations are empty. receive operation in mode ?1?: when the 554d is in fifo mode (fcr bit-0 = logic 1, fcr bit-3 = logic 1) and the trigger level has been reached, or a receive time out has occurred, the - rxrdy pin will go to a logic 0. once activated, it will go to a logic 1 after there are no more characters in the fifo. fcr bit 4-5: not used - initialized to a logic 0. fcr bit 6-7: (logic 0 or cleared is the default condi- tion, rx trigger level = 1) these bits are used to set the trigger level for the receive fifo interrupt. an interrupt is generated when the number of charac- ters in the fifo equals the programmed trigger level. however the fifo will continue to be loaded until it is full. bit-7 bit-6 rx fifo trigger level 00 1 01 4 10 8 11 14 interrupt status register (isr) the 554d provides four levels of prioritized interrupts to minimize external software interaction. the inter- rupt status register (isr) provides the user with six interrupt status bits. performing a read cycle on the isr will provide the user with the highest pending interrupt level to be serviced. no other interrupts are acknowledged until the pending interrupt is serviced. whenever the interrupt status register is read, the interrupt status is cleared. however it should be noted that only the current pending interrupt is cleared by the read. a lower level interrupt may be seen after reread- ing the interrupt status bits. the interrupt source table 7 (below) shows the data values (bit 0-5) for the four prioritized interrupt levels and the interrupt sources associated with each of these interrupt levels: table 7, interrupt source table priority [ isr bits ] level bit-5 bit-4 bit-3 bit-2 bit-1 bit-0 source of the interrupt 1 000110 lsr (r eceiver line status register) 2 000100 rxrdy (received data ready) 2 001100 rxrdy (receive data time out) 3 000010 txrdy ( transmitter holding register empty) 4 000000 msr (m odem status register)
ST16C554/554d/68c554 21 rev. 3.10 isr bit-0: logic 0 = an interrupt is pending and the isr contents may be used as a pointer to the appropriate interrupt service routine. logic 1 = no interrupt pending. (normal default condi- tion) isr bit 1-3: (logic 0 or cleared is the default condition) these bits indicate the source for a pending interrupt at interrupt priority levels 1, 2, and 3 (see interrupt source table). isr bit 4-5: not used - initialized to a logic 0. isr bit 6-7: (logic 0 or cleared is the default condition) these bits are set to a logic 0 when the fifo is not being used. they are set to a logic 1 when the fifos are enabled. line control register (lcr) the line control register is used to specify the asynchronous data communication format. the word length, the number of stop bits, and the parity are selected by writing the appropriate bits in this register. lcr bit 0-1: (logic 0 or cleared is the default condi- tion) these two bits specify the word length to be transmit- ted or received. bit-1 bit-0 word l ength 00 5 01 6 10 7 11 8 lcr bit-2: (logic 0 or cleared is the default condition) the length of stop bit is specified by this bit in conjunction with the programmed word length. bit-2 word l ength stop bit length (bit time(s)) 0 5,6,7,8 1 1 5 1-1/2 1 6,7,8 2 lcr bit-3: parity or no parity can be selected via this bit. logic 0 = no parity. (normal default condition) logic 1 = a parity bit is generated during the transmis- sion, receiver checks the data and parity for transmis- sion errors. lcr bit-4: if the parity bit is enabled with lcr bit-3 set to a logic 1, lcr bit-4 selects the even or odd parity format. logic 0 = odd parity is generated by forcing an odd number of logic 1?s in the transmitted data. the receiver must be programmed to check the same format. (normal default condition) logic 1 = even parity is generated by forcing an even the number of logic 1?s in the transmitted. the receiver must be programmed to check the same format. lcr bit-5: if the parity bit is enabled, lcr bit-5 selects the forced parity format. lcr bit-5 = logic 0, parity is not forced. (normal default condition) lcr bit-5 = logic 1 and lcr bit-4 = logic 0, parity bit is forced to a logical 1 for the transmit and receive data. lcr bit-5 = logic 1 and lcr bit-4 = logic 1, parity bit is forced to a logical 0 for the transmit and receive data.
ST16C554/554d/68c554 22 rev. 3.10 lcr lcr lcr parity selection bit-5 bit-4 bit-3 x x 0 no parity 0 0 1 odd parity 0 1 1 even parity 1 0 1 force parity ?1? 1 1 1 forced parity ?0? lcr bit-6: when enabled the break control bit causes a break condition to be transmitted (the tx output is forced to a logic 0 state). this condition exists until disabled by setting lcr bit-6 to a logic 0. logic 0 = no tx break condition. (normal default condition) logic 1 = forces the transmitter output (tx) to a logic 0 for alerting the remote receiver to a line break condition. lcr bit-7: not used - initialized to a logic 0. modem control register (mcr) this register controls the interface with the modem or a peripheral device. mcr bit-0: logic 0 = force -dtr output to a logic 1. (normal default condition) logic 1 = force -dtr output to a logic 0. mcr bit-1: logic 0 = force -rts output to a logic 1. (normal default condition) logic 1 = force -rts output to a logic 0. mcr bit-2: this bit is used in the loopback mode only. in the loopback mode this bit is use to write the state of the modem -ri interface signal via -op1. mcr bit-3: ( used to control the modem -cd signal in the loopback mode.) logic 0 = forces int (a-d) outputs to the three state mode during the 16 mode. (normal default condition) in the loopback mode, sets -op2 (-cd) internally to a logic 1. logic 1 = forces the int (a-d) outputs to the active mode during the 16 mode. in the loopback mode, sets -op2 (-cd) internally to a logic 0. mcr bit-4: logic 0 = disable loopback mode. (normal default condition) logic 1 = enable local loopback mode (diagnostics). mcr bit 5-7: not used - initialized to a logic 0. line status register (lsr) this register provides the status of data transfers between. the 554d and the cpu. lsr bit-0: logic 0 = no data in receive holding register or fifo. (normal default condition) logic 1 = data has been received and is saved in the receive holding register or fifo. lsr bit-1: logic 0 = no overrun error. (normal default condition) logic 1 = overrun error. a data overrun error occurred in the receive shift register. this happens when addi- tional data arrives while the fifo is full. in this case the previous data in the shift register is overwritten. note that under this condition the data byte in the receive shift register is not transfered into the fifo, therefore the data in the fifo is not corrupted by the error. lsr bit-2: logic 0 = no parity error. (normal default condition) logic 1 = parity error. the receive character does not have correct parity information and is suspect. in the fifo mode, this error is associated with the character at the top of the fifo. lsr bit-3: logic 0 = no framing error. (normal default condition) logic 1 = framing error. the receive character did not
ST16C554/554d/68c554 23 rev. 3.10 have a valid stop bit(s). in the fifo mode this error is associated with the character at the top of the fifo. lsr bit-4: logic 0 = no break condition. (normal default condi- tion) logic 1 = the receiver received a break signal (rx was a logic 0 for one character frame time). in the fifo mode, only one break character is loaded into the fifo. lsr bit-5: this bit is the transmit holding register empty indi- cator. this bit indicates that the uart is ready to accept a new character for transmission. in addition, this bit causes the uart to issue an interrupt to cpu when the thr interrupt enable is set. the thr bit is set to a logic 1 when a character is transferred from the transmit holding register into the transmitter shift register. the bit is reset to logic 0 concurrently with the loading of the transmitter holding register by the cpu. in the fifo mode this bit is set when the transmit fifo is empty; it is cleared when at least 1 byte is written to the transmit fifo. lsr bit-6: this bit is the transmit empty indicator. this bit is set to a logic 1 whenever the transmit holding register and the transmit shift register are both empty. it is reset to logic 0 whenever either the thr or tsr contains a data character. in the fifo mode this bit is set to one whenever the transmit fifo and transmit shift register are both empty. lsr bit-7: logic 0 = no error. (normal default condition) logic 1 = at least one parity error, framing error or break indication is in the current fifo data. this bit is cleared when lsr register is read. modem status register (msr) this register provides the current state of the control interface signals from the modem, or other peripheral device that the 554d is connected to. four bits of this register are used to indicate the changed information. these bits are set to a logic 1 whenever a control input from the modem changes state. these bits are set to a logic 0 whenever the cpu reads this register. msr bit-0: logic 0 = no -cts change (normal default condition) logic 1 = the -cts input to the 554d has changed state since the last time it was read. a modem status interrupt will be generated. msr bit-1: logic 0 = no -dsr change. (normal default condition) logic 1 = the -dsr input to the 554d has changed state since the last time it was read. a modem status interrupt will be generated. msr bit-2: logic 0 = no -ri change. (normal default condition) logic 1 = the -ri input to the 554d has changed from a logic 0 to a logic 1. a modem status interrupt will be generated. msr bit-3: logic 0 = no -cd change. (normal default condition) logic 1 = indicates that the -cd input to the has changed state since the last time it was read. a modem status interrupt will be generated. msr bit-4: -cts (active high, logical 1). normally msr bit-4 bit is the compliment of the -cts input. however in the loopback mode, this bit is equivalent to the rts bit in the mcr register. msr bit-5: dsr (active high, logical 1). normally this bit is the compliment of the -dsr input. in the loopback mode, this bit is equivalent to the dtr bit in the mcr register. msr bit-6: ri (active high, logical 1). normally this bit is the compliment of the -ri input. in the loopback mode this bit is equivalent to the op1 bit in the mcr register.
ST16C554/554d/68c554 24 rev. 3.10 msr bit-7: cd (active high, logical 1). normally this bit is the compliment of the -cd input. in the loopback mode this bit is equivalent to the op2 bit in the mcr register. scratchpad register (spr) the ST16C554d provides a temporary data register to store 8 bits of user information. ST16C554d external reset conditions registers reset state ier ier bits 0-7=0 isr isr bit-0=1, isr bits 1-7=0 lcr lcr bits 0-7=0 mcr mcr bits 0-7=0 lsr lsr bits 0-4=0, lsr bits 5-6=1 lsr, bit 7=0 msr msr bits 0-3=0, msr bits 4-7= input signals fcr fcr bits 0-7=0 signals reset state tx a-d high -rts a-d high -dtr a-d high -rxrdy high -txrdy low
ST16C554/554d/68c554 25 rev. 3.10 symbol parameter limits limits units con ditions 3.3 5.0 min max min max ac electrical characteristics t a =0 - 70c (-40 - +85c for industrial grade packages), vcc=3.3 - 5.0 v 10% unless otherwise specified. t 1w, t 2w clock pulse duration 17 17 ns t 3w oscillator/clock frequency 8 24 mhz t 6s address setup time 5 0 ns t 7d -ior delay from chip select 10 10 ns t 7w -ior strobe width 35 25 ns t 7h chip select hold time from -ior 0 0 ns t 9d read cycle delay 40 30 ns t 12d delay from -ior to data 35 25 ns t 12h data disable time 25 35 15 ns t 13d -iow delay from chip select 10 10 ns t 13w -iow strobe width 35 25 ns t 13h chip select hold time from -iow 0 0 ns t 15d write cycle delay 40 30 ns t 16s data setup time 20 15 ns t 16h data hold time 5 5 ns t 17d delay from -iow to output 50 40 ns 100 pf load t 18d delay to set interrupt from modem 40 35 ns 100 pf load input t 19d delay to reset interrupt from -ior 40 35 ns 100 pf load t 20d delay from stop to set interrupt 1 1 rclk t 21d delay from -ior to reset interrupt 45 40 ns 100 pf load t 22d delay from stop to interrupt 45 40 ns t 23d delay from initial int reset to transmit 8 24 8 24 rclk start t 24d delay from -iow to reset interrupt 45 40 ns t 25d delay from stop to set -rxrdy 1 1 rclk t 26d delay from -ior to reset -rxrdy 45 40 ns t 27d delay from -iow to set -txrdy 45 40 ns t 28d delay from start to reset -txrdy 8 8 rclk t 30s address setup time 10 10 ns t 30w chip select strobe width 40 40 ns t 30h address hold time 15 15 ns t 30d read cycle delay 70 70 ns t 31d delay from -cs to data 15 15 ns t 31h data disable time 15 ns t 32s write strobe setup time 10 10 ns t 32h write strobe hold time 10 10 ns t 32d write cycle delay 70 70 ns
ST16C554/554d/68c554 26 rev. 3.10 symbol parameter limits limits units con ditions 3.3 5.0 min max min max ac electrical characteristics t a =0 - 70c (-40 - +85c for industrial grade packages), vcc=3.3 - 5.0 v 10% unless otherwise specified. t 33s data setup time 20 15 ns t 33h data hold time 10 10 ns t r reset pulse width 40 40 ns n baud rate devisor 1 2 16 -1 1 2 16 -1 rclk
ST16C554/554d/68c554 27 rev. 3.10 symbol parameter limits limits units con ditions 3.3 5.0 min max min max absolute maximum ratings supply range 7 volts voltage at any pin gnd - 0.3 v to vcc +0.3 v operating temperature -40 c to +85 c storage temperature -65 c to 150 c package dissipation 500 mw dc electrical characteristics t a =0 - 70c (-40 - +85c for industrial grade packages), vcc=3.3 - 5.0 v 10% unless otherwise specified. v ilck clock input low level -0.3 0.6 -0.5 0.6 v v ihck clock input high level 2.4 vcc 3.0 vcc v v il input low level -0.3 0.8 -0.5 0.8 v v ih input high level 2.0 2.2 vcc v v ol output low level on all outputs 0.4 v i ol = 5 ma v ol output low level on all outputs 0.4 v i ol = 4 ma v oh output high level 2.4 v i oh = -5 ma v oh output high level 2.0 v i oh = -1 ma i il input leakage 10 10 m a i cl clock leakage 10 10 m a i cc avg power supply current 3 6 ma c p input capacitance 5 5 pf r in internal pull-up resistance 3 15 k w note: see the symbol description table, for a listing of pins having internal pull-up resistors.
ST16C554/554d/68c554 28 rev. 3.10 general write timing in 68 mode general read timing in 68 mode a0-a4 -cs r/-w d0-d7 t30s t30h t30w t32s t32h t32d t33s t33h 8654-wd-1 -cs r/-w d0-d7 t30s t30h t31h t31d t30d t30w 8654-rd-1 a0-a4
ST16C554/554d/68c554 29 rev. 3.10 general write timing in 16 mode general read timing in 16 mode a0-a2 -cs -iow d0-d7 t6s t13w t13d t13h t15d t16s t16h x552-wd-1 valid address active active data a0-a2 -cs -ior d0-d7 t6s t7w t7d t7h t9d t12d t12h x552-rd-1 active data valid address active
ST16C554/554d/68c554 30 rev. 3.10 external clock timing modem input/output timing -iow -rts -dtr -cd -cts -dsr int -ior -ri t17d t18d t18d t19d t18d x552-md-1 active active change of state change of state active active active change of state change of state change of state active active t3w t1w t2w external clock x654-ck-1
ST16C554/554d/68c554 31 rev. 3.10 receive timing stop bit parity bit data bits (5-8) d0 d1 d2 d3 d4 d5 d6 d7 5 data bits 6 data bits 7 data bits start bit rx next data start bit int -ior t20d t21d 16 baud rate clock x552-rx-1 active active
ST16C554/554d/68c554 32 rev. 3.10 receive timing in fifo mode receive ready timing in none fifo mode stop bit parity bit data bits (5-8) d0 d1 d2 d3 d4 d5 d6 d7 start bit rx next data start bit -rxrdy -ior t25d t26d x552-rx-2 active data ready active stop bit parity bit data bits (5-8) d0 d1 d2 d3 d4 d5 d6 d7 start bit rx first byte that reaches the trigger level -rxrdy -ior t25d t26d x552-rx-3 active data ready active
ST16C554/554d/68c554 33 rev. 3.10 transmit timing stop bit parity bit data bits (5-8) d0 d1 d2 d3 d4 d5 d6 d7 5 data bits 6 data bits 7 data bits start bit tx next data start bit int t22d t24d 16 baud rate clock x552-tx-1 -iow t23d active active tx ready active
ST16C554/554d/68c554 34 rev. 3.10 transmit ready timing in none fifo mode stop bit parity bit data bits (5-8) d0 d1 d2 d3 d4 d5 d6 d7 start bit tx next data start bit -txrdy t28d x654-tx-2 -iow t27d byte #1 active active transmitter ready transmitter not ready d0-d7
ST16C554/554d/68c554 35 rev. 3.10 transmit ready timing in fifo mode stop bit parity bit data bits (5-8) d0 d1 d2 d3 d4 d5 d6 d7 5 data bits 6 data bits 7 data bits start bit tx -iow d0-d7 -txrdy byte #16 t28d t27d x552-tx-3 fifo full active
ST16C554/554d/68c554 36 rev. 3.10
package dimensions a 0.102 0.130 2.60 3.30 0.102 0.134 2.60 3.40 a 1 0.002 0.010 0.05 0.25 0.002 0.014 0.05 0.35 a 2 0.100 0.120 2.55 3.05 0.100 0.120 2.55 3.05 b 0.009 0.015 0.22 0.38 0.009 0.015 0.22 0.38 c 0.005 0.009 0.13 0.23 0.005 0.009 0.13 0.23 d 0.904 0.923 22.95 23.45 0.931 0.951 23.65 24.15 d 1 0.783 0.791 19.90 20.10 0.783 0.791 19.90 20.10 e 0.667 0.687 16.95 17.45 0.695 0.715 17.65 18.15 e 1 0.547 0.555 13.90 14.10 0.547 0.555 13.90 14.10 e 0.025 6 bsc 0.65 bsc 0.0256 bsc 0.65 bsc l 0.029 0.040 0.73 1.03 0.026 0.037 0.65 0.95 a 0 7 0 7 0 7 0 7 100 lead plastic quad fl a t p ack (14 mm x 20 mm, qfp) rev. 2.00 symbol min max min max inches millimeters 80 51 50 31 1 3 0 81 100 d d 1 e e 1 b e a 2 a a 1 a seatin g plane note: the control dimension is the millimeter column l c min max min max inches millimeters 1.6 mm form 1.95 mm form
package dimensions a 0.055 0.063 1.40 1.60 a 1 0.002 0.006 0.05 0.15 a 2 0.053 0.057 1.35 1.45 b 0.005 0.009 0.13 0.23 c 0.004 0.008 0.09 0.20 d 0.465 0.480 1 1.80 12.20 d 1 0.390 0.398 9.90 10.10 e 0.02 0 bsc 0.5 0 bsc l 0.018 0.030 0.45 0.75 a 0 7 0 7 64 lead thin quad fl a t p ack (10 x 10 x 1.4 mm, tqfp) rev. 2.00 symbol min max min max inches millimeters 48 33 32 17 1 1 6 49 64 d d 1 d d 1 b e a 2 a a 1 a seatin g plane note: the control dimension is the millimeter column l c
package dimensions 68 lead plastic leaded chip carrier (plcc) rev. 1.00 1 d d 1 d d 1 d 3 d 2 a a 1 2 6 8 a 0.165 0.200 4.19 5.08 a 1 0.090 0.130 2.29 3.30 a 2 0.020 . 0.51 b 0.013 0.021 0.33 0.53 b 1 0.026 0.032 0.66 0.81 c 0.008 0.013 0.19 0.32 d 0.985 0.995 25.02 25.27 d 1 0.950 0.958 24.13 24.33 d 2 0.890 0.930 22.61 23.62 d 3 0.80 0 typ. 20.3 2 typ. e 0.050 bsc 1.27 bsc h1 0.042 0.056 1.07 1.42 h2 0.042 0.048 1.07 1.22 r 0.025 0.045 0.64 1.14 symbol min max min max inches millimeters b a 2 b 1 e seating plane d 3 note: the control dimension is the inch column 45 x h2 45 x h1 c r
notice exar corporation reserves the right to make changes to the products contained in this publication in order to im- prove design, performance or reliability. exar corporation assumes no responsibility for the use of any circuits de- scribed herein, conveys no license under any patent or other right, and makes no representation that the circuits are free of patent infringement. charts and schedules contained here in are only for illustration purposes and may vary depending upon a user's specific application. while the information in this publication has been carefully checked; no responsibility, however, is assumed for inaccuracies. exar corporation does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reasonably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. products are not authorized for use in such applications unless exar corporation receives, in writing, assurances to its satisfaction that: (a) the risk of injury or damage has been minimized; (b) the user assumes all such risks; (c) potential liability of exar corporation is adequately protected under the circum- stances. copyright 1994 exar corporation reproduction, in part or whole, without the prior written consent of exar corporation is prohibited.

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